Methods of forming a gated device

ABSTRACT

This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device includes a pair of source/drain regions having a channel region therebetween. A gate is received proximate the channel region between the source/drain regions. The gate has a gate width between the source/drain regions. A gate dielectric is received intermediate the channel region and the gate. The gate dielectric has at least two different regions along the width of the gate. The different regions are characterized by different materials which are effective to define the two different regions to have different dielectric constants k. Other aspects and implementations are contemplated.

TECHNICAL FIELD

This invention relates to gated field effect devices, and to methods offorming gated field effect devices.

BACKGROUND OF THE INVENTION

Gated field effect devices, such as transistors, are utilized inintegrated circuitry, such as logic circuitry and memory circuitry.Exemplary memory includes static random access memory (SRAM), dynamicrandom access memory (DRAM) and floating gate programmable read-onlymemories (i.e., PROMs, EPROMs and EEPROMs). In a gated field effectdevice, a conductive gate is received proximate a channel regiontypically formed in lightly doped semiconductive material. Source/drainregions are received on opposing sides of the channel region. Uponapplication of a suitable threshold voltage to the gate, an electricfield is created in the channel region, enabling or causing current toflow through the channel region from the source region to the drainregion. Alternately by way of example only, field effect devices havealso been utilized to establish fields beneath conductive gates forcreating isolation between circuitry components within a semiconductivesubstrate.

Field effect devices include at least one conductive gate region and atleast one gate dielectric region interposed between the conductive gateregion and the semiconductive channel region. A common and predominantlyused gate dielectric material has been SiO₂. Yet, continued increase incircuit density and reduction in size of field effect device gateconstructions have reached the point where the thickness of silicondioxide gate dielectric layers has become so small that leakagecurrents, reliability and defects have become problematic. Accordingly,alternate materials have been utilized, for example insulative metaloxides.

Regardless, the substrates after gate fabrication are typicallysubjected to a reoxidation step which oxidizes a portion of the gateimmediately adjacent the dielectric surface at the outer edges of theconductive gate material. Such effectively creates a so-called “smilinggate” structure in which tiny bird's beak structures are formed at thebottom corners of the gate stack. Such reoxidation can help to repairdamage to dielectric and silicon surfaces resulting from the anisotropicetch typically utilized to form the gate stack and, as well, reduces hotelectron degradation in the device in operation. An effect is toincrease the thickness of the gate dielectric at the gate edges asopposed to the center of the gate. This has the apparent effect oflowering the electric field within the semiconductive material of thesubstrate at the source/drain edges, thereby reducing hot electrondegradation.

While the invention was motivated in addressing the above identifiedissues, it is in no way so limited. The invention is only limited by theaccompanying claims as literally worded, without interpretative or otherlimiting reference to the specification, and in accordance with thedoctrine of equivalents.

SUMMARY

The invention includes gated field effect devices, and methods offorming gated field effect devices. In one implementation, a gated fieldeffect device includes a pair of source/drain regions having a channelregion therebetween. A gate is received proximate the channel regionbetween the source/drain regions. The gate has a gate width between thesource/drain regions. A gate dielectric is received intermediate thechannel region and the gate. The gate dielectric has at least twodifferent regions along the width of the gate. The different regions arecharacterized by different materials which are effective to define thetwo different regions to have different dielectric constants k.

In one implementation, a method of forming a gated device includesdepositing a first metal containing gate dielectric over one of a gateregion or a channel region. The gate region or channel region has awidth over which the first metal containing gate dielectric isdeposited. A width portion of the metal containing gate dielectricoverlying the one of the gate region or the channel region is doped witha second metal different from the first metal effective to form at leasttwo different gate dielectric regions along the width characterized bydifferent materials effective to define the two different gatedielectric regions to have different dielectric constants k. The otherportion of the gate region or the channel region is provided over thegate dielectric. A pair of source/drain regions is provided proximatethe channel region.

In one implementation, A method of forming a gated device includesdepositing a first gate dielectric material over a channel region of asemiconductor substrate. A conductive gate material is formed over thefirst gate dielectric material. The conductive gate material ispatterned effective to form a gate over the first gate dielectricmaterial. The gate comprises opposing sides defining a gate widththerebetween. The first gate dielectric material is isotropically etchedfrom at least one side of the gate effective to recess the first gatedielectric material on the at least one side to under the gate. Afterthe isotropically etching, a second gate dielectric material differentfrom the first gate dielectric material is deposited to within therecess beneath the gate. The second gate dielectric material has adifferent dielectric constant k than that of the first gate dielectricmaterial. A pair of source/drain regions is provided proximate thechannel region.

In one implementation, a method of forming a gated device includesproviding a substrate comprising one of a gate region or a channelregion. The gate region or channel region comprises a width. A firstportion of the width of the one of the gate region or the channel regionis masked while depositing a first gate dielectric material over asecond portion of the width of the one of the gate region or the channelregion. The second portion of the width of the one of the gate region orthe channel region is masked while depositing a second gate dielectricmaterial different from the first gate dielectric material over thefirst portion of the width of the one of the gate region or the channelregion. The first and second gate dielectric materials are characterizedby different dielectric constants k. The other of the gate region or thechannel region is provided over the first and second gate dielectricmaterials. A pair of source/drain regions is provided proximate thechannel region.

Other aspects and implementations are contemplated.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

FIG. 1 is a diagrammatic sectional view of a device in accordance withan aspect of the invention.

FIG. 2 is a diagrammatic sectional view of another device in accordancewith an aspect of the invention.

FIG. 3 is a diagrammatic sectional view of another device in accordancewith an aspect of the invention.

FIG. 4 is a diagrammatic sectional view of another device in accordancewith an aspect of the invention.

FIG. 5 is a diagrammatic sectional view of a substrate fragment inprocess in accordance with an aspect of the invention.

FIG. 6 is a view of the FIG. 5 substrate fragment at a processingsubsequent to that depicted by FIG. 5.

FIG. 7 is a view of the FIG. 6 substrate fragment at a processingsubsequent to that depicted by FIG. 6.

FIG. 8 is a view of the FIG. 7 substrate fragment at a processingsubsequent to that depicted by FIG. 7.

FIG. 9 is a diagrammatic sectional view of another substrate fragment inprocess in accordance with an aspect of the invention.

FIG. 10 is a view of the FIG. 9 substrate fragment at a processingsubsequent to that depicted by FIG. 9.

FIG. 11 is a view of the FIG. 10 substrate fragment at a processingsubsequent to that depicted by FIG. 10.

FIG. 12 is a diagrammatic sectional view of another substrate fragmentin process in accordance with an aspect of the invention.

FIG. 13 is a view of the FIG. 12 substrate fragment at a processingsubsequent to that depicted by FIG. 12.

FIG. 14 is a view of the FIG. 13 substrate fragment at a processingsubsequent to that depicted by FIG. 13.

FIG. 15 is a view of the FIG. 14 substrate fragment at a processingsubsequent to that depicted by FIG. 14.

FIG. 16 is a view of the FIG. 15 substrate fragment at a processingsubsequent to that depicted by FIG. 15.

FIG. 17 is a diagrammatic sectional view of another substrate fragmentin process in accordance with an aspect of the invention.

FIG. 18 is a view of the FIG. 17 substrate fragment at a processingsubsequent to that depicted by FIG. 17.

FIG. 19 is a view of the FIG. 18 substrate fragment at a processingsubsequent to that depicted by FIG. 18.

FIG. 20 shows a diagrammatic view of computer illustrating an exemplaryapplication of the present invention.

FIG. 21 is a block diagram showing particular features of themotherboard of the FIG. 20 computer.

FIG. 22 shows a high level block diagram of an electronic systemaccording to an exemplary aspect of the present invention.

FIG. 23 shows a simplified block diagram of an exemplary deviceaccording to an aspect of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

This disclosure of the invention is submitted in furtherance of theconstitutional purposes of the U.S. Patent Laws “to promote the progressof science and useful arts” (Article 1, Section 8).

A first embodiment gated field effect device is indicated generally inFIG. 1 with reference numeral 10. Such is depicted as being formedrelative to a base substrate 12, for example bulk monocrystallinesilicon. Alternate substrates are contemplated, including semiconductorsubstrates, for example semiconductor-on-insulator substrates or othersubstrates, and whether existing or yet-to-be developed. In the contextof this document, the term “semiconductor substrate” or “semiconductivesubstrate” is defined to mean any construction comprising semiconductivematerial, including, but not limited to, bulk semiconductive materialssuch as a semiconductive wafer (either alone or in assemblies comprisingother materials thereon), and semiconductive material layers (eitheralone or in assemblies comprising other materials). The term “substrate”refers to any supporting structure, including, but not limited to, thesemiconductive substrates described above.

A pair of source/drain regions 14, 16 is formed within substrate 12, anda channel region 18 is received therebetween. Source/drain regions 14,16 comprise highest conductivity doped regions 20 and 22, respectively,and lightly doped drain regions 24 and 26, respectively. Additionalregions, for example halo implant regions, could of course be utilized,as well as any other source/drain region or component thereof whetherexisting or yet-to-be developed. For example and by way of example only,the source/drain regions might be fabricated to include or consist ofmaterials other than conductively doped semiconductive material, beformed in semiconductor-on-insulator layers, be fabricated to compriseelevated source/drain regions, etc. Alternate channel regions and otherconfigurations are also of course contemplated.

Gated field effective device 10 comprises a gate 28 received proximatechannel region 18 between source/drain regions 14, 16. A gate dielectric30 is received intermediate channel region 18 and gate 28. In thedepicted preferred embodiment, gate 28 is shown as comprising twoconductive material layers 36 and 38. Exemplary thicknesses for layers36 and 38 are 500 Angstroms and 400 Angstroms, respectively. By way ofexample only, an exemplary material for conductive layer/region 36 isconductively doped polysilicon, and an exemplary material 38 is one thatis of higher conductivity than material 36, with tungsten or tungstensilicide being but two examples. Gate 28 comprises or defines a gatewidth 35 between source drain regions 14, 16. Exemplary optional andpreferred insulative sidewall spacers 32 and 34 have been formed byanisotropic etching about sidewalls of gate 28. By way of example onlypreferred materials include silicon dioxide and silicon nitride.

Gate dielectric 30 comprises at least two different regions along width35 of gate 28. The different regions are characterized by differentmaterials effective to define such two different regions to havedifferent dielectric constants k. In the depicted exemplary andpreferred embodiment, gate dielectric 30 comprises at least three, andonly three, different regions 42, 44 and 46. Further in one preferredembodiment, region 44 comprises a central region which is laterallycentered along width 35 of gate 28, with regions 42 and 46 comprising apair of regions received adjacent to and straddling central region 44.In one preferred embodiment, central region 44 is of a differentmaterial than either of straddling regions 42 and 46 effective to definecentral region 44 to have a different dielectric constant k than that ofeither of straddling regions 42 and 46. In one preferred embodiment,straddling regions 42 and 46 comprise from 10% to 25% of width 35 ofgate 28.

In one preferred embodiment, different regions 42, 44 and 46 arerespectively characterized by a uniform dielectric constant kthereacross in a direction along width 35 of gate 28. In one exemplaryalternate embodiment, at least one of the different regions of the gatedielectric is characterized by variable dielectric constant k across theone region in a direction along the width of the gate. In one exemplaryembodiment, each of straddling regions 42 and 46 is of higher dielectricconstant k than that of central region 44. In an alternate embodiment,each of straddling regions 42 and 46 is of lower dielectric constant kthan that of central region 44. In one exemplary embodiment, straddlingregions 42 and 46 are of the same composition material and dielectricconstant k. Accordingly by way of example only in such instance, gatedielectric 30 is characterized by at least three different regions alongwidth 35 of gate 28 further characterized by two different dielectricconstant materials preferably having uniform dielectric constant kthereacross in a direction along width 35 of gate 28. In the depictedpreferred embodiment, regions 42 and 46 are received proximatesource/drain regions 14, 16, respectively, and also as shown, preferablyextend to source/drain regions 14, 16, respectively. In one preferredembodiment, straddling regions 42 and 46 are of different compositionmaterial and dielectric constant k.

In one preferred embodiment, at least one of the different gatedielectric regions is characterized by a uniform dielectric constant kthereacross in a direction along the width of the gate which spans atleast 50% of the width of the gate. In the illustrated exemplary FIG. 1embodiment, central region 44 constitutes but one such exemplary region.

As described in the “Background” section above, source/drain reoxidationtends to thicken the gate dielectric by forming gate oxide regions atthe source/drain edges of the gate, leaving the central portion of thegate dielectric over the channel region at the as-grown thickness. Inthe current state of the art, an advantageous effect of such results inlowering the electric field at the source/drain regions, therebyreducing hot carrier effects and increasing device lifetimes. Analternative, or addition thereto, would be to lower the dielectricconstant of the gate dielectric at the source/drain edges by varyinggate dielectric composition to provide an effectively thicker gatedielectric at the gate edges even though the physical thickness of thegate dielectric may be unchanged. Such could have the same effect oflowering the electric field at the source/drain edges. Alternately ifdesired, dielectric constant by material modification could be utilizedto raise the dielectric constant at the source/drain edges, or elsewherealong some portion of the gate width.

Increasing or decreasing the dielectric constant can be accomplished byproviding the different composition material regions by, for exampleonly, doping desired regions of the gate dielectric material. Forexample in one implementation, consider that a hafnium oxide gatedielectric can be doped with elemental aluminum such that the effectivedielectric constant is reduced from that of pure hafnium oxide.Alternately by way of example only, an aluminum oxide gate can be dopedwith elemental hafnium for increasing the effective dielectric constantfrom that of aluminum oxide alone. By way of example only, additionalexamples include doping tantalum oxide with niobium to result in anincrease of k over that of pure tantalum oxide, silicon doping ofhafnium oxide to reduce k from that over pure hafnium oxide, andzirconium doping of barium strontium titanate to result in lower k thanthat over pure barium strontium titanate. Of course, any dopant might beisovalent, acceptor-type or donor-type, and depending on the desire andmodification of the effective dielectric constant.

In accordance with one implementation, the different gate dielectricmaterials for the different material regions comprise oxides. In oneimplementation, the different oxides comprise Hf_(x)Al_(y)O_(z), where“z” is greater than zero, and “x” and “y” range from 0 to 1 with atleast one of “x” and “y” being greater than zero. In one exemplaryimplementation, the different oxides comprise Ta_(x)Nb_(y)O_(z), where“z” is greater than zero, and “x” and “y” range from 0 to 1 with atleast one of “x” and “y” being greater than zero. In one implementation,the different oxides comprise Hf_(x)Si_(y)O_(z), where “z” is greaterthan zero, and “x” and “y” range from 0 to 1 with at least one of “x”and “y” being greater than zero. In one implementation, the differentoxides comprise Ba_(x)Sr_(y)Ti_(z)O₃, where “x”, “y” and “z” range from0 to 1 with at least one of “x”, “y” and “z” being greater than zero. Inone implementation, the different oxides comprise ZrO_(x), where xranges from 1 to 2.

FIG. 1 depicts an example wherein one different material region 44 iscentered laterally between a pair of different composition regions 42and 46 relative to gate 28. By way of example only, FIG. 2 provides analternate example embodiment gated field effect device 10 a. Likenumerals from the first-described embodiment are utilized whereappropriate, with differences being indicated with the suffix “a”. Here,a region 44a is depicted as not being centered laterally between a pairof regions 42 a and 46 a. Of course, alternate embodiments arecontemplated having different sizes and orientations for the depictedregions, including more or fewer of the illustrated three regions.Further and by way of example only, FIG. 3 depicts an alternateembodiment gated field effect device 10 b. Like numerals from thefirst-described embodiment are utilized where appropriate, withdifferences being indicated with the suffix “b”, or with differentnumerals. Here, gate dielectric 30 b is comprised of only two differentregions 43 and 47 characterized by different materials effective todefine two different regions having different dielectric constants k.FIG. 3 depicts regions 43 and 47 as being of the same width along widthdimension 35 off gate 28, although such regions could of course be ofdifferent widths.

The above-depicted exemplary embodiments illustrate the respective gatedielectrics being of constant thickness along the width of therespective gates. By way of example only, a preferred thickness rangefor gate dielectrics 30, 30 a, and 30 b is from 20 Angstroms to 80Angstroms. Further by way of example only, FIG. 4 depicts an alternateembodiment gated field effect device 10 c wherein the gate dielectric isof variable thickness along the width of the gate. Like numerals fromthe first-described embodiment are utilized where appropriate, withdifferences being indicated with the suffix “c”. Here, gate dielectric30 c depicts different material regions 42 c and 44 c having beensubjected to source/drain re-oxidation such that a conventionalthickened region thereof results at the gate edges/sidewalls. Of course,only one of the edges might be thickened or any different variablethickness might be provided along the width of the gate for gatedielectric 30 c.

The above-described embodiments depict substantially planar orhorizontally-oriented gated field effect devices. Of course, vertical,annular, or any other configuration is contemplated, whether existing oryet-to-be-developed, with the above merely being exemplary preferredembodiments.

Additional aspects of the invention contemplate fabricating various ofthe above-described and depicted devices, as well as methods of forminggated devices as literally claimed including independent of structuralattributes as described above. By way of example only, a firstembodiment method of forming a gated device is described with referenceto FIGS. 5-8. FIG. 5 depicts a substrate fragment 50 comprisingsemiconductor material 52, for example bulk monocrystalline silicon. Forpurposes of the continuing discussion, substrate 52 comprises one of agate region or a channel region, with a channel region 54 beingdepicted. Such region 54 may not, and typically will not, be completelydefined or perhaps at all defined by lateral or length boundaries atthis point in the process. Regardless, the ultimate channel region 54can be considered as comprising a width 55 which will ultimately bedefined for the gated device. A first metal containing gate dielectric56 is deposited over channel region 54. An exemplary thickness for layer56 is from 20 Angstroms to 80 Angstroms. Any of the above-describedmetal and/or silicon oxides are exemplary preferred materials.

Referring to FIG. 6, some width portion 58 of metal containing gatedielectric 56 overlying channel region 54 has been doped with a secondmetal different from the first metal effective to form at least twodifferent gate dielectric regions 58 and 59, 60 along width 55. Such atleast two different gate dielectric regions are characterized bydifferent materials effective to define at least two different of gatedielectric regions 58 and 59, 60 to have different dielectric constantsk. Again, any of the above exemplary described materials are preferred.For example and by way of example only, a single metal oxide mightinitially be deposited, such as hafnium oxide. Any one or more of thedepicted width portions 59, 58 and 60 could thereafter be doped withanother metal, for example aluminum, such that at least two gatedielectric regions characterized as described are formed. Alternately byway of example only, layer 56 might be deposited to comprise multiplemetals beyond a first metal, with some width portion of the metalcontaining gate dielectric 56 overlying channel region 54 being dopedwith one of the existing or additional metals of a multiple metalcontaining dielectric layer. Accordingly, the “second” metal might alsobe incorporated in the gate dielectric as initially deposited. Furtherof course, more than two metals might be utilized. Preferred doping toproduce the described at least two different material regions might beby any of ion implantation, gas phase diffusion, plasma phase diffusionor any other method, whether existing or yet-to-be developed, andutilizing appropriate masking or directing of the doping metal ormetals.

At some point in such a method of forming a gated device, the other ofthe gate region or the channel region is provided over the gatedielectric, and a pair of source/drain regions are also providedproximate the channel region. FIG. 7 depicts conductive gate layers 36and 38 having been deposited over gate dielectric 56, with preferredattributes being as described above in connection with the firstdescribed embodiment having layers 36 and 38. FIG. 8 depicts subsequentprocessing thereof to define the depicted gate outline having sidewallspacers, thereby, in this example, producing the exemplary FIG. 1embodiment gated field effect device 10. Of course, the described methodcould be utilized to form any of the other FIGS. 2-4, or other, gatedfield effect devices. Other preferred attributes in the method offabricating the device as just-described include any of theabove-described attributes in the fabrication of the exemplary FIGS. 1-4embodiments.

FIGS. 5-8 depict an exemplary embodiment wherein the first metalcontaining gate dielectric is deposited over the channel region. By wayof example only, FIGS. 9-11 depict an exemplary alternate embodimentsubstrate fragment 50 d. Like numerals from the first-describedembodiment are utilized where appropriate, with differences beingindicated with the suffix “d”, or with different numerals. Substratefragment 50 d is comprised of a base substrate 52 d made up of one ormore conductive, semiconductive and/or insulating materials. Aninsulating layer 61 has been formed thereover. An opening or trough 62has been provided therein and filled with some suitable conductive gatematerial 64. In this exemplary embodiment, conductive gate material 64defines or comprises a suitable gate region having an exemplary width55. A first metal containing gate dielectric 56 d is deposited over gateregion 64.

Referring to FIG. 10, at least one of width portions 59 d , 58 d and 60d of metal containing gate dielectric 56 d overlying gate region 64 hasbeen doped with a second metal different from the first metal effectiveto form the illustrated at least two different gate dielectric regions58 d and 59 d, 60 d.

Referring to FIG. 11, a semiconductor layer 66 has been deposited. Suchhas been processed, patterned and otherwise formed to comprisesource/drain regions 67 and 68, and a channel region 69 therebetween.

Further by way of example only, another exemplary method of forming agated device is described with reference to FIGS. 12-16. FIG. 12 depictsa substrate fragment 70 comprising, for example, a bulk semiconductorsubstrate 72. Substrate 72 comprises a channel region 54, for example asdescribed above in connection with substrate fragment in FIG. 5. A firstgate dielectric material 74 has been deposited over channel region 54 ofsemiconductor substrate 72. Conductive gate material 75 has been formedover first gate dielectric material 74, with exemplary layers 36 and 38as described above being shown to encompass conductive gate material 75.

Referring to FIG. 13, conductive gate material 75 has been patternedeffective to form a gate 76 over first gate dielectric material 74. Gate76 can be considered as comprising opposing sides 78 and 80 defining agate width 55 therebetween. In the depicted exemplary preferredembodiment, first gate dielectric material 74 is patterned commensuratewith the patterning of conductive gate material 75 effective to formfirst gate material 74 to comprise opposing sides 82 and 84 which arelaterally coincident with gate sides 78 and 80, respectively. However,the invention also contemplates leaving some or all of material 74 overthe source/drain regions at this point in the process. In one preferredembodiment, FIG. 13 also depicts the formation of lightly doped drainregions 24 and 26.

Referring to FIG. 14, the first gate dielectric material has beenisotropically etched from at least one side of the gate effective torecess the gate dielectric material on the at least one side to underthe gate. In the depicted preferred embodiment, isotropic etching offirst gate dielectric material 74 has been conducted from both sides 78and 80 of gate 76 effective to recess first gate dielectric material 74on both such sides to be received beneath gate 76 within the lateralconfines of gate sides 78 and 80. Exemplary preferred isotropic etchingincludes wet etching. For example, and by way of example only, wheregate dielectric material 74 comprises hafnium oxide, layer 38 comprisestungsten or tungsten silicide, and layer 36 comprises doped polysilicon,an exemplary isotropic etching chemistry for hafnium oxide to producethe exemplary construction of FIG. 14 includes wet etching with HF orphosphoric acid, or dry etch with Cl₂ based chemistries at elevatedtemperatures up to 300° C.

Referring to FIG. 15, after the isotropic etching, a second gatedielectric material 86 different from first gate dielectric material 74has been deposited to within the recesses previously formed beneath gate76. Second gate dielectric material 86 is characterized as having adifferent dielectric constant k than that of first gate dielectricmaterial 74. Again, and by way of example only, any of theabove-described exemplary preferred materials can be utilized. Exemplarypreferred techniques for the deposition include chemical vapordeposition and atomic layer deposition towards achieving the depictedrecess filling of FIG. 15.

Referring to FIG. 16, subsequent processing is depicted whereby, in onepreferred embodiment, second gate dielectric material 86 has beenanisotropically etched to form insulative field effect device sidewallspacers 88 and 90. Further and ultimately as shown, a pair ofsource/drain regions 92 and 94 have been formed proximate channel region54. In the exemplary depicted embodiment, such encompass lightly dopeddrain regions 24 and 26, respectively, and highest dopant concentrationregions 96 and 98, respectively. In the depicted and described exemplaryembodiment, the formation of highest dopant concentration regions 96 and98 of source/drain regions 92 and 94, respectively, is conducted afterboth of the described isotropic etching of dielectric material 74 andthe depositing of second gate dielectric material 86. Processing is, ofcourse, contemplated where the providing of the highest dopantconcentration regions of the source/drain regions is provided before oneor both of the isotropic etching and depositing of the second gatedielectric material. By way of example only, other attributes arepreferably as described above in conjunction with the FIGS. 1-4embodiments.

Yet another exemplary preferred method of forming a gated device inaccordance with aspects of the invention is described with reference toFIGS. 17-19 in conjunction with a semiconductor substrate fragment 100.By way of example only, such comprises a bulk semiconductor substrate,for example monocrystalline silicon. Such comprises one of a gate regionor a channel region, with an exemplary channel region 54 being shownhaving a width 55, for example as described above in connection withFIG. 5. For purposes of the continuing discussion, substrate fragment100 can be considered as comprising a first portion 104 and a secondportion 105. In the depicted FIG. 17 embodiment, first portion 104comprises a portion of width 55 of channel region 54. Such portionthereof has been masked while depositing a first gate dielectricmaterial 110 over second portion 105 of channel region 54. Exemplarypreferred materials are any of those described above in conjunction withthe FIG. 1 embodiment. An exemplary preferred technique for masking anddepositing material 110 includes depositing material 110, thenpatterning with photoresist, followed by etching.

Referring to FIG. 18, second portion 105 of width 55 of channel region54 has been masked while depositing a second gate dielectric material115, different from first gate dielectric material 110, which isreceived over first portion 104 of width 55 of channel region 54. Thefirst and second gate dielectric materials 110 and 115 are characterizedby different dielectric constants k. Again, exemplary preferredmaterials are those described above in connection with the FIG. 1embodiment.

Ultimately, the other of the gate region or the channel region isprovided over the first and second gate dielectric materials, and a pairof source/drain regions is provided proximate the channel region. By wayof example only, FIG. 19 depicts the fabrication of gated field effectdevice 10 of the exemplary first described embodiment. Other exemplarypreferred attributes are as described above with respect to the FIGS.1-4 embodiments.

FIGS. 17-19 depict that the described maskings of the first and secondportions occur over the channel region. Of course, this aspect of theinvention also contemplates maskings of the first and second portionsoccurring over a gate region, for example analogous processing to thatdepicted and described in conjunction with FIGS. 9-11.

FIG. 20 illustrates generally, by way of example but not by way oflimitation, an embodiment of a computer system 400 according to anaspect of the present invention. Computer system 400 includes a monitor401 or other communication output device, a keyboard 402 or othercommunication input device, and a motherboard 404. Motherboard 404 cancarry a microprocessor 406 or other data processing unit, and at leastone memory device 408. Memory device 408 can comprise various aspects ofthe invention described above. Memory device 408 can comprise an arrayof memory cells, and such array can be coupled with addressing circuitryfor accessing individual memory cells in the array. Further, the memorycell array can be coupled to a read circuit for reading data from thememory cells. The addressing and read circuitry can be utilized forconveying information between memory device 408 and processor 406. Suchis illustrated in a block diagram of the motherboard 404 as shown inFIG. 21. In such block diagram, the addressing circuitry is illustratedas 410 and the read circuitry is illustrated as 412.

In particular aspects of the invention, memory device 408 can correspondto a memory module. For example, single in-line memory modules (SIMMs)and dual in-line memory modules (DIMMs) may be used in implementationsthat utilize the teachings of the present invention. The memory devicecan be incorporated into any of a variety of designs that providedifferent methods of reading from and writing to memory cells of thedevice. One such method is the page mode operation. Page mode operationsin a DRAM are defined by the method of accessing a row of a memory cellarrays and randomly accessing different columns of the array. Datastored at the row and column intersection can be read and output whilethat column is accessed.

An alternate type of device is the extended data output (EDO) memorythat allows data stored at a memory array address to be available asoutput after the addressed column has been closed. This memory canincrease some communication speeds by allowing shorter access signalswithout reducing the time in which memory output data is available on amemory bus. Other alternative types of devices include SDRAM, DDR SDRAM,SLDRAM, VRAM and Direct RDRAM, as well as others such as SRAM or Flashmemories.

FIG. 22 illustrates a simplified block diagram of a high-levelorganization of various embodiments of an exemplary electronic system700 which, by way of example only, can be incorporated with aspects ofthe present invention. System 700 can correspond to, for example, acomputer system, a process control system, or any other system thatemploys a processor and associated memory. Electronic system 700 hasfunctional elements, including a processor or arithmetic/logic unit(ALU) 702, a control unit 704, a memory device unit 706 and aninput/output (I/O) device 708. Generally, electronic system 700 willhave a native set of instructions that specify operations to beperformed on data by the processor 702 and other interactions betweenthe processor 702, the memory device unit 706 and the I/O devices 708.The control unit 704 coordinates all operations of the processor 702,the memory device 706 and the I/O devices 708 by continuously cyclingthrough a set of operations that cause instructions to be fetched fromthe memory device 706 and executed. In various embodiments, the memorydevice 706 includes, but is not limited to, random access memory (RAM)devices, read-only memory (ROM) devices, and peripheral devices such asa floppy disk drive and a compact disk CD-ROM drive. One of ordinaryskill in the art will understand, upon reading and comprehending thisdisclosure, that any of the illustrated electrical components arecapable of being fabricated to include DRAM or other memory cells inaccordance with various aspects of the present invention.

FIG. 23 is a simplified block diagram of a high-level organization ofvarious embodiments of an exemplary electronic system 800. The system800 includes a memory device 802 that has an array of memory cells 804,address decoder 806, row access circuitry 808, column access circuitry810, read/write control circuitry 812 for controlling operations, andinput/output circuitry 814. The memory device 802 further includes powercircuitry 816, and sensors 820, such as current sensors for determiningwhether a memory cell is in a low-threshold conducting state or in ahigh-threshold non-conducting state. The illustrated power circuitry 816includes power supply circuitry 880, circuitry 882 for providing areference voltage, circuitry 884 for providing a first wordline withpulses, circuitry 886 for providing a second wordline with pulses, andcircuitry 888 for providing a bitline with pulses. The system 800 alsoincludes a processor 822, or memory controller for memory accessing.

The memory device 802 receives control signals from the processor 822over wiring or metallization lines. The memory device 802 is used tostore data that is accessed via I/O lines. It will be appreciated bythose skilled in the art that additional circuitry and control signalscan be provided, and that the memory device 802 has been simplified tohelp focus on the invention. At least one of the processor 822 or memorydevice 802 can include a capacitor construction in a memory device ofthe type described previously herein.

The various illustrated systems of this disclosure are intended toprovide a general understanding of various applications for thecircuitry and structures of the present invention, and are not intendedto serve as a complete description of all the elements and features ofan electronic system using memory cells in accordance with aspects ofthe present invention. One of ordinary skill in the art will understandthat the various electronic systems can be fabricated in single-packageprocessing units, or even on a single semiconductor chip, in order toreduce the communication time between the processor and the memorydevice(s).

Applications for memory cells can include electronic systems for use inmemory modules, device drivers, power modules, communication modems,processor modules, and application-specific modules, and may includemultilayer, multichip modules. Such circuitry can further be asubcomponent of a variety of electronic systems, such as a clock, atelevision, a cell phone, a personal computer, an automobile, anindustrial control system, an aircraft, and others.

In compliance with the statute, the invention has been described inlanguage more or less specific as to structural and methodical features.It is to be understood, however, that the invention is not limited tothe specific features shown and described, since the means hereindisclosed comprise preferred forms of putting the invention into effect.The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1-60. (canceled)
 61. A method of forming a gated device, comprising:depositing a first metal containing gate dielectric over one of a gateregion or a channel region, the gate region or channel region comprisinga width over which the first metal containing gate dielectric isdeposited; doping a width portion of the metal containing gatedielectric overlying the one of the gate region or the channel regionwith a second metal different from the first metal effective to form atleast two different gate dielectric regions along the widthcharacterized by different materials effective to define the twodifferent gate dielectric regions to have different dielectric constantsk; providing the other of the gate region or the channel region over thegate dielectric; and providing a pair of source/drain regions proximatethe channel region.
 62. The method of claim 61 wherein the dopingcomprises ion implantation.
 63. The method of claim 61 wherein thedoping comprises gas phase diffusion.
 64. The method of claim 61 whereinthe doping comprises plasma phase diffusion.
 65. The method of claim 61wherein the first metal containing gate dielectric is deposited over thechannel region.
 66. The method of claim 61 wherein the first metalcontaining gate dielectric is deposited over the gate region.
 67. Themethod of claim 61 wherein the doping is effective to form only twodifferent gate dielectric regions for the device.
 68. The method ofclaim 61 wherein the doping is effective to form at least threedifferent gate dielectric regions for the device.
 69. The method ofclaim 68 wherein the doping is effective to form only three differentgate dielectric regions for the device.
 70. A method of forming a gateddevice, comprising: depositing a first gate dielectric material over achannel region of a semiconductor substrate; forming a conductive gatematerial over the first gate dielectric material; patterning theconductive gate material effective to form a gate over the first gatedielectric material, the gate comprising opposing sides defining a gatewidth therebetween; isotropically etching the first gate dielectricmaterial from at least one side of the gate effective to recess thefirst gate dielectric material on the at least one side to under thegate; after the isotropically etching, depositing a second gatedielectric material different from the first gate dielectric material towithin the recess beneath the gate, the second gate dielectric materialhaving a different dielectric constant k than that of the first gatedielectric material; and forming a pair of source/drain regionsproximate the channel region.
 71. The method of claim 69 comprisingpatterning the first gate dielectric material commensurate with saidpatterning of the conductive gate material effective to form the firstgate dielectric material to comprise opposing sides which are laterallycoincident with the gate sides.
 72. The method of claim 69 wherein theisotropically etching etches the first gate dielectric material fromboth sides of the gate effective to recess the first gate dielectricmaterial to under the gate of both gate sides.
 73. The method of claim69 comprising patterning the first gate dielectric material commensuratewith said patterning of the conductive gate material effective to formthe first gate dielectric material to comprise opposing sides which arelaterally coincident with the gate sides; and wherein the isotropicallyetching etches the first gate dielectric material from both sides of thegate effective to recess the first gate dielectric material to under thegate of both gate sides.
 74. The method of claim 69 wherein theisotropically etching comprises wet etching.
 75. The method of claim 69wherein the providing of the source/drain regions comprises forminghighest dopant concentration of said regions after the isotropicallyetching.
 76. The method of claim 69 wherein the providing of thesource/drain regions comprises forming highest dopant concentration ofsaid regions before the isotropically etching.
 77. The method of claim69 wherein the providing of the source/drain regions comprises forminghighest dopant concentration of said regions after the depositing of thesecond gate dielectric material.
 78. The method of claim 69 wherein theproviding of the source/drain regions comprises forming highest dopantconcentration of said regions before the depositing of the second gatedielectric material.
 79. The method of claim 69 further comprisinganisotropically etching the second gate dielectric material effective toform electrically insulative sidewall spacers over sidewalls of thegate.
 80. A method of forming a gated device, comprising: providing asubstrate comprising one of a gate region or a channel region, the gateregion or channel region comprising a width; masking a first portion ofthe width of the one of the gate region or the channel region whiledepositing a first gate dielectric material over a second portion of thewidth of the one of the gate region or the channel region; masking thesecond portion of the width of the one of the gate region or the channelregion while depositing a second gate dielectric material different fromthe first gate dielectric material over the first portion of the widthof the one of the gate region or the channel region, the first andsecond gate dielectric materials being characterized by differentdielectric constants k; providing the other of the gate region or thechannel region over the first and second gate dielectric materials; andproviding a pair of source/drain regions proximate the channel region.81. The method of claim 80 wherein the maskings of the first and secondportions occur over the channel region.
 82. The method of claim 80wherein the maskings of the first and second portions occur over thegate region.